Reverse Engineering Challenge

Event Overview: The Reverse Engineering Challenge is a technical competition designed to evaluate participants’ understanding of signal processing, embedded systems, and circuit modeling by reconstructing hidden or compiled system designs. Participants will be provided with black-box artifacts such as protected MATLAB/Simulink models, embedded firmware binaries, and SPICE netlists/output characteristics. Their task is to reverse engineer and reproduce equivalent models that closely match the original system behavior. This event emphasizes system-level thinking, analytical reasoning, and engineering intuition, rather than brute-force trial-and-error. Objectives: To test participants understanding on fundamentals in signal and systems , circuit design and coding To encourage model abstraction and behavioral equivalence To bridge theory with applied system reconstruction To promote ethical reverse engineering strictly for educational purposes Problem Domains: The competition consists of three independent tracks. Participants may attempt one or more tracks. Track A: MATLAB / Simulink Reverse Engineering: Participants will be given: A protected Simulink model (.slx/.mdl) Task: Reconstruct a functionally equivalent Simulink or MATLAB model that reproduces: Input–output behavior Frequency response Time-domain characteristics Systems may include: Filters Modulation schemes Control loops Track B: Embedded Binary Reconstruction: Participants will be given: Compiled embedded firmware (.hex, .elf, .bin) Limited I/O description Task: Reproduce: The underlying algorithm (in C / MATLAB / Python) Signal processing or control logic Timing behavior (within tolerance) No disassembly is required; inference must be based on observed behavior. Track C: SPICE Model Characterization: Participants will be given: Equivalent block level characteristic graphs and overall characteristic graphs along with the inputs Task: Reconstruct the circuit with a given functionality via characteristic graphs in your own unique way. Circuits may include: Operational Amplifier (Op-Amp) MOSFET’s Phase-Locked Loop (PLL) Resistor Capacitor Only I/O characteristics are deemed to be important, not the different interpretations of the circuit themselves. Participants will be judged based on the correctness of the i/o characteristic graphs solely evaluated by organizers. Rules And Regulations: General Rules: This is a team-based event (1–5 members per team). Cracking the protected files may result in direct eviction. Only behavioral equivalence is evaluated, not exact structural duplication. Any form of plagiarism or sharing of solutions results in disqualification. Each participant must be registered under a single team. The organizers reserve the right to interpret, modify, or enforce the rules, and their decision shall be final in all matters including discrepancies, disputes, or rule exploitation. NOTE: People are expected to bring their own extension boxes. Allowed Tools: MATLAB / Simulink LTspice Disallowed Actions: Using disassemblers or decompilers on provided binaries Extracting protected Simulink internals using exploits Modifying provided files Evaluation Criteria: Functional Accuracy — 60% Design Explanation & Novelity — 20% Clean Modeling & Documentation — 20% Deliverables: Each team must submit: Reconstructed model or source files Simulation results (plots/screenshots) A short technical report (2–3 pages) explaining: Observations Assumptions Modeling approach Trade-offs Target Audience: Undergraduate students (ECE, EE, EEE, Robotics etc) Signal processing and VLSI enthusiasts Embedded systems and analog design learners Event Duration: Total duration: 4–6 hours Each track evaluated independently